Conventionally, in a semiconductor device comprising a semiconductor memory such as RAM (Random Access Memory), defective bits contained in the memory are salvaged to improve the extraction rate. When doing this, setting the salvage address information for salvaging the defective bits is performed using a programmable fuse or the like. Also, when an externally input address matches the salvage address, the semiconductor device uses a spare memory cell to salvage the defective bits.
Recently, the demand for high-speed memory access of semiconductor memory is ever increasing. One kind of signal propagation path that determines the access speed is a signal path that compares the salvage-address information that is stored in the fuse with an externally input address. In this case, in order to make it possible to increase speed without performing this address comparison, shift redundancy has been proposed. In shift redundancy, a switch is located in the memory-bit selection line, and by shifting the relationship between the selection line and external-input address one by one to the next value, the defective bits are separated from the signal path so it is not necessary to compare addresses.
When salvaging defective bits, in order to more precisely salvage defective bits using the shift redundancy, it is necessary to decrease the size of the salvage unit. As a result, when looking at the entire memory, a very large number of fuses becomes necessary in order to record the number of salvage units and the salvage addresses for each salvage unit. Moreover, the number of signals that are generated from the fuse information for controlling the selection line switch becomes large. Therefore, it is desired that in order to reduce the wiring channels the switch and fuses be adjacent to each other. However, when they are adjacent to each other, the fuses become scattered throughout the entire chip, so the time required for alignment and the like when fuses are turned OFF increases, and the cost for manufacturing the semiconductor-memory device increases.
Therefore, a semiconductor device has been disclosed in Patent Document 1, for example, as a device that comprises means for decreasing the wiring channel. This semiconductor device brings all of the fuses on the chip together in one location, and has a register group next to the fuses that reads the fuse signals, as well as has a register group in a comparison circuit that compares the input address signals with the fuse signals, and is such that both register groups are separated from each other. Also, both register groups are constructed into a daisy chain by having one data-signal line and one clock signal for read/write control of the registers, in order to reduce the number of wiring channels.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2000-182394A (FIG. 1)
[Non-patent Document 1] Jan M. Rabaey, et. al, “Digital Integrated Circuits”, Prentice Hall, December 2002